1. Field of the Invention
The present invention relates to a dynamic type semiconductor memory device of a lower voltage side power supply voltage sensing and a voltage direct reference cell writing system.
2. Description of Related art
In recent years, along with advances in power saving of cellular phones and other system products, a semiconductor memory device indispensable for constituting such a system has been required to operate at lower voltage. For example, a DRAM (Dynamic Random Access Memory) operating at a low voltage of VDD=0.85 V or lower starts to become widely used. On the other hand, the semiconductor memory device operating at lower voltage is required to have performances such as a wide voltage operating range, a wide temperature operating range, and an unspecified noise resistance. In order to satisfy such required performances, the DRAM operating at lower voltage starts to employ a lower voltage side power supply voltage sensing (e.g., GND sensing) and direct reference cell writing system.
Re-distribution of charges accumulated in a memory cell capacitance in a DRAM does not start until a word line voltage becomes higher by a threshold voltage Vt than a bit line voltage. This means that when a slew rate of a signal is large or a word line is long, the word line becomes a critical path. For example, if a bit line is precharged to the voltage of VDD/2 (e.g. 1.5 V) with a signal having the slew rate of 1 V/ns in a conventional VDD/2 bit line precharge system, an extra delay of 750 ps occurs. On the other hand, in a GND precharge system using a reference cell, although a reference cell area (e. g., 1.5% of 16 megabits) is required, an equalizing margin of a bit line and Vgs of a sense amplifier transistor can be largely saved. Therefore, timing for activating a sense amplifier can be sped up.
In the precharge system using a reference cell, a reference cell pair is precharged to the voltage of VDD/2 in accordance with complementary write data during an active operation. In this case, twice operations of the reference cells such as a charging operation and an equalizing operation are performed so as to make a cycle time larger. As a method of preventing such increase in cycle time, there is a direct reference cell writing system. In the direct reference cell writing system, immediately after activation of a sense amplifier, a selected reference cell is turned off, and a connection between the reference cell and a bit line is disconnected. Then, the voltage of VDD/2 is directly written to a reference cell capacitance through a transistor. Thus, the charging operation and the equalizing operation are integrated, resulting in improvement of the cycle time. According to the direct reference cell writing system, not only the improvement of the cycle time, but a ratio of a signal amount and a retention time are optimized, and a high-speed signal margin is obtained by a reference voltage converted into a constant voltage.
A DRAM of the general direct reference cell writing system is described in, for example, “A 300 MHz Multi-Banked eDRAM Macro Featuring GND Sense, Bit-Line Twisting and Direct Reference Cell Write” (ISSCC 2002/Session 9/DRAM AND FERROELECTRIC MEMORIES/9.3).
Referring to FIG. 1, the general GND sensing and direct reference cell writing system used for a DRAM will be described. FIG. 1 is a circuit diagram illustrating a configuration of a part of a DRAM employing the direct reference cell writing system according to a conventional technique. The DRAM illustrated in FIG. 1 includes a latch type differential sense amplifier circuit 101, a precharge circuit 102, a reference voltage supply circuit 403, and a memory cell array 404 of memory cells, each of which is connected to bit lines BT and BC. The bit lines BT and BC may be collectively referred to as a bit line pair BT and BC.
The latch type differential sense amplifier circuit 101 operates between a latch type differential sense amplifier circuit supply voltage SETP and a ground voltage GND, and amplifies a voltage difference between the bit lines BT and BC.
The precharge circuit 102 has an equalizing function and a precharging function. Specifically, when a supplied precharge control signal EQP is in a high level, the precharge circuit 102 connects the bit lines BT and BC to a ground voltage GND to precharge them to a GND voltage (lower voltage side power supply voltage). Alternatively, if the precharge control signal EQP is in a low level, the precharge circuit 102 disconnects the connection between the bit lines BT and BC and the ground voltage GND,
The reference voltage supply circuit 403 includes reference cell capacitances 8 and 15, and N-channel MOS transistors 10, 11, 12, and 14.
The reference cell capacitance 8 is connected to the ground voltage GND at one end thereof (opposite electrode node 28), and to the NMOS transistors 10 and 11 at the other end thereof (reference cell node 9) The reference cell capacitance 8 (reference cell node 9) is connected to a VDD/2 node (power supply node of a reference voltage (VDD/2)) through the NMOS transistor 10, and to the bit line BT through the NMOS transistor 11. The NMOS transistor 10 controls an electrical connection between the reference cell node 9 and the bit line BT in response to a signal supplied from a reference word line RFWL0 connected to a gate thereof. The NMOS transistor 11 controls an electrical connection between the reference cell node 9 and the VDD/2 node in response to a direct write control signal REQP (hereinafter to be referred to as a write signal REQP) supplied to a gate thereof.
The reference cell capacitance 15 is connected to the ground voltage GND at one end thereof (opposite electrode node 29), and to the NMOS transistors 12 and 14 at the other end thereof (reference cell node 13). The reference cell capacitance 15 (reference cell node 13) is connected to the power supply node VDD/2 (voltage value of VDD/2) through the NMOS transistor 14, and to the bit line BC through the NMOS transistor 12. The NMOS transistor 12 controls an electrical connection between the reference cell node 13 and the bit line BC in response to a signal supplied from a reference word line RFWL1 connected to a gate thereof. The NMOS transistor 10 controls an electrical connection between the reference cell node 9 and the power supply node VDD/2 in response to the write signal REQP supplied to a gate thereof.
In the reference voltage supply circuit 403, charges are stored in the reference cell capacitance 8 or 15 (hereinafter to be collectively referred to as a reference memory cell) from the VDD/2 node response to the write signal REQP. Also, the charges stored in the reference memory cell are re-distributed to the bit line pair BT and BC in response to the signals supplied to the reference word lines RFWL0 and REWL1.
The memory cell array 404 includes memory cell capacitances 16 and 21, and N-channel MOS transistors 18 and 19. The memory cell capacitance 16 is connected to the ground voltage GND at one end thereof (opposite electrode node 30), and to the bit line BT at the other end thereof (memory cell node 17) through the NMOS transistor 18. The NMOS transistor 18 controls an electrical connection between the memory cell node 17 and the bit line BT in response to a signal supplied from a word line WL1 connected to a gate thereof. The memory cell capacitance 21 is connected to the GND voltage at one end thereof (opposite electrode node 31), and to the bit line BC at the other end thereof (memory cell node 20) through the NMOS transistor 19. The NMOS transistor 19 controls an electrical connection between the memory cell node 20 and the bit line BC in response to a signal supplied from a word line WL0 connected to a gate thereof.
In the memory cell array 404, charges stored in the memory cell capacitance 16 or 21 (hereinafter to be collectively referred to as a memory cell) are read from the bit line pair BT and BC (read), or charges are stored in the memory cell from the bit line pair BT and BC (write). At this time, a memory cell subjected to the read or write is selected by activating the word line WL0 or WL1 connected thereto.
In the DRAM illustrated in FIG. 1, the opposite electrode nodes 28 and 29 of the reference memory cells and the opposite electrode nodes 30 and 31 of the memory cells are all connected to the ground voltage GND. For this reason, if a high level voltage is applied to the reference cell node 9 or 13, or memory cell node 17 or 20, a voltage difference corresponding to the power supply voltage VDD is applied between the reference cell node 9 to 13 applied with the high level voltage and the corresponding opposite electrode node 28 to 31 applied with the ground voltage GND. Accordingly, a capacitance insulating film forming the memory cell capacitance is applied with the voltage difference corresponding to the power supply voltage VDD; and thereby may be broken. On the other hand, although not illustrated, similarly when any of the opposite electrode nodes is applied with the power supply voltage VDD, if a corresponding one of the memory cell nodes is applied with a low level voltage, a capacitance insulating film is applied with a voltage corresponding to the power supply voltage VDD, and thereby broken. From the above, it is necessary to connect a plate potential supply circuit 107 adapted to supply a voltage of ½ of the power supply voltage VDD to the opposite electrode nodes 18 to 29 as illustrated in FIG. 2.
FIG. 2 is a circuit diagram illustrating a configuration of a part of a DRAM of a direct reference cell writing system, which uses the plate potential supply circuit 107 and is mounted in a general product. The DRAM illustrated in FIG. 2 includes a reference voltage supply circuit 303 and a memory cell array 304 of which respective opposites electrode nodes 28 to 31 are connected to the plate potential supply circuit 107, instead of the reference voltage supply circuit 403 and memory cell array 404 in the DRAM illustrated in FIG. 1. The plate potential supply circuit 107 fixes the opposite electrode nodes 28 to 31 to ½ of the power supply voltage VDD, and therefore a voltage applied to the memory cell capacitance 16 or 21, or reference cell capacitance 8 or 15 becomes ½ of VDD or less. For this reason, in the DRAM illustrated in FIG. 2, any capacitance insulating film is not broken, differently from the DRAM illustrated in FIG, 1.
Also, as a related technique, a DRAM including a circuit adapted to control a voltage of a charge accumulation node of a dummy cell during a bit line precharge period is described in Japanese Patent Application Publication (JP-A-Heisei 11-026720).
If a memory size of the DRAM illustrated in FIG. 2 becomes larger (e.g., 16 megabits or more), wiring lines from the plate potential supply circuit 107 to far ends of the opposite electrode nodes 28 to 31 become longer, and have therefore a high impedance.
Recently, the opposite electrode nodes 28 to 31 connected with such high impedance are driven with a lower power supply voltage of 0.85 V of a lower power consumption amount. For this reason, charging speeds from the reference cell nodes 9 and 13 to the reference cell capacitances 8 and 15 in response to current variations are delayed, and coupling noises due to voltage variations of the reference cell nodes 9 and 13 are superimposed to the memory cell node 17 and 20 through the opposed electrode nodes 28 and 29, 30 and 31. Similarly, coupling noises due to voltage variations of the memory cell nodes 17 and 20 are superimposed to the reference cell nodes 9 and 13 through the opposite electrode nodes 28, 29, 30, and 31. From the above, voltage values of the memory cell nodes 17 and 20 and reference cell nodes 9 and 13 connected to the same bit lines are likely to be fluctuated by the influence of the respective voltage variations.
For example, upon charging/discharging to/from the memory cell or the reference cell, the coupling noises caused by the voltage variations of the memory cell nodes 17 and 20 and reference cell nodes 9 and 13 influence each other. Therefore, voltages of the opposite electrode nodes 28, 29, 30, and 31 upon restoring or sensing of the reference cell capacitances 8 and 15 and memory cell capacitances 16 and 21 are varied. Along with this, the voltage difference between the bit lines BT and BC decreases, and a sensing margin by the latch type differential sense amplifier circuit 101 is deteriorated.
Causes of the deterioration of the sensing margin in the DRAM illustrated in FIG. 2 will be described in detail. Here, a case will be described that high level data “1” is written (cell H write) to, or the high level data “1” is read (cell H read) from the memory cell (cell capacitance 21). When the reference word line RFWL0 is activated after the bit lines BT and BC have been precharged to the ground voltage GND, a voltage of the reference cell node 9 starts to change from the voltage of VDD/2 to the ground voltage GND. At this time, voltages of the opposite electrode nodes 28 to 31 also drop from the voltage of VDD/2 to the ground voltage GND due to coupling. The plate potential supply circuit 107 operates to restore the voltages of the opposite electrode nodes 28 to 31 to the voltage of VDD/2 in response to the voltage drops of the opposite electrode nodes 28 to 31. Subsequently, the write signal REQP is activated to restore the voltage of the reference cell node 9 from the ground voltage GND to the voltage of VDD/2, and the voltage of the opposite electrode node 28 becomes the voltage of VDD/2 due to coupling. However, if the plate potential supply circuit 107 has a low response speed, it operates to further raise the voltages of the opposite electrode nodes 28 to 31. In this case, the voltages of the opposite electrode nodes 28 to 31 become the voltage of VDD/2 or more. Therefore, an amount of charges accumulated in the memory cell becomes lower than an expectation value of the cell H (the charge amount to be detected as the high level data “1”). If such a state occurs during a period during which the word line WL0 is activated, a write error or a rewrite error occurs.
Also, when a low level data “0” is written (cell L write), or read (cell L read), an amount of charges accumulated in the memory cell may become larger than an expectation value of the cell L (charge amount to be detected as the low level data “0”).
Specifically, when the reference word line RFWL0 is activated, the bit line BT precharged to the ground voltage GND varies the voltage of the reference cell node 9 from the voltage of VDD/2 to the ground voltage GND. For this reason, the voltage of the opposite electrode node 28 of the reference cell also drops from the voltage of VDD/2 to the ground voltage GND due to coupling. Subsequently, when the write control signal REQP transits to a high level, the voltage of the reference cell node 9 is restored from the voltage GND to the voltage of VDD/2. However, a time to restore the voltage of the reference cell node 9 to the voltage of VDD/2 may be long. Therefore, the voltage may not be restored to the voltage of VDD/2 before the activated word line falls. In particular, in a high speed cycle, the voltage of the reference cell node 9 at the time at which the word line falls may not be restored to the voltage of VDD/2. In such a case, due to coupling noise from the reference cell node 9 at the voltage of VDD/2 or lower, the voltages of the opposite electrode nodes 30 and 31 of the memory cell also become the voltage of VDD/2 or lower. For this reason, the amount of charges accumulated in the memory cell becomes larger than the expectation value of the cell L.
Further, in the DRAM illustrated in FIG. 2, a signal amount that is an expected charge amount accumulated in the bit lines upon read/write may be short. For example, in a cell H read or a cell H write cycle, when the reference word line RFWL0 is activated, the voltage of the reference cell node 9 is varied from the voltage of VDD/2 to the voltage GND. Therefore, the voltage of the opposite electrode node 28 of the reference cell is also decreased from the voltage of VDD/2 to the voltage GND due to coupling. This voltage variation propagates to the opposite electrode nodes 30 and 31 of the memory cells. Because the word line WL0 is activated, the voltage of the bit line BC is decreased due to coupling to decrease a voltage difference upon amplification. In such a state, when a read or write operation is started, a voltage variation due to the voltage variation at the reference cell node 9 decreases the voltage of the bit line BC through the memory cell node 20. Such a voltage variation of the bit line BC deteriorates the sensing margin of the amplifier. Similarly, when the reference word line RFWL1 is activated, the voltage variation of the bit line BT deteriorates the sensing margin of the amplifier.